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| TC9404FNG TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC9404FNG - Modulation System DA Converter with Analog Filter TC9404FNG is a 2'nd order - modulation system 1-bit DA converter incorporating an 8-times over sampling digital filter and analog filter developed for digital audio equipment. Because the IC includes an analog filter, it can output a direct analog waveform, thus reducing the size and cost of the DA converter. Features * * * * * * * * * * * Built-in 8-times over sampling digital filter Low-voltage operates (3.0 V) possible Built-in digital de-emphasis filter In serial mode, output amplitude can be set in 128 steps of resolution using microcontroller command. In parallel mode, soft mute can beset for the output signal in 64 steps in 20 ms. Built-in LR common digital zero detection output circuit Over sampling ratio (OSR) of - modulation circuit is 192 fs Support double speed operation Sampling frequency: 44.1 kHz, 32 kHz, 48 kHz Built-in 3'rd order analog filter The digital filter and DA converter characteristics are as follows: Weight: 0.14 g (typ.) P-SSOP24-300-0.65A Digital Filter (fs = 44.1 kHz) DA Converter (VDD = 5 V) 1 2006-04-27 TC9404FNG Pin Assignment Block Diagram 2 2006-04-27 TC9404FNG Pin Function Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Symbol VDD T1 P/ S VDA RO GNDA VR GNDA LO VDA ZD GNDD MCK GNDX XI I/O I I Function Digital block power supply pin. Test pin. Always set to "Low" level. Parallel/serial mode select pin. Analog power supply pin. Right channel analog signal output pin. Analog GND pin. Reference voltage pin. Analog GND pin. Left channel analog signal output pin. Analog power supply pin. Digital zero detection output pin. Digital GND pin. System clock output pin. Crystal oscillator GND pin. Remarks O O O O I Crystal oscillator connecting pin. Generates the clock required by the system. 16 17 18 XO VDX LATCH (BS) SHIFT (EMP) ATT (SM) O I Crystal oscillator power supply pin. Serial mode: Data latch signal input pin. Parallel mode: De-emphasis filter mode select pin. Serial mode: Shift clock input pin. Parallel mode: De-emphasis filter control pin. Serial mode: Data input pin. Parallel mode: Soft mute control pin. Standard/double speed operation mode switching pin. Standard operation at "H", double speed operation at "L". Audio data input pin. Bit clock input pin. LR clock input pin. Schmitt input 19 I Schmitt input 20 I Schmitt input 21 22 23 24 HS DATA BCK LRCK I I I I 3 2006-04-27 TC9404FNG Description of Block Operations 1. Crystal Oscillator Circuit and Timing Generator The clock required for internal operations is generated by connecting a crystal and condensers as shown in the diagram below. The IC will also operate when a system clock is input from an external source through the XI pin (pin 15). However, in this situation, due consideration must be given to the fact that waveform characteristics, such as jitter and rising/falling characteristics of the system clock, significantly affect the DA converter's noise distortion and the S/N ratio. CL = 10~33 pF Use a crystal with a low CI value and favorable start-up characteristics. Figure 1 Crystal Oscillation Circuit Configuration (when in the 384 fs mode) The timing generator generates the clocks and process timing signals required for such functions as digital filtering and de-emphasis filtering. 2. Data Input Circuit DATA and the LRCK are loaded to the LSI internal shift registers on the BCK signal rising edge. It is consequently necessary for the DATA and LRCK signals to be synchronized and input on the BCK signal falling edge as indicated in the timing example below. Also, as DATA has been designed so that the 16 bits before the change point of LRCK are regarded as valid data, the data must be input with Right-justified mode when the BCK is 48 fs or 64 fs, as shown in Figure 2b. Figure 2a Example of Input Timing Chart 4 2006-04-27 TC9404FNG Figure 2b Example of Input Timing Chart 3. Digital Filter The 8-times oversampling IIR digital filter eliminates the noise returned from outside the bandwidth during standard and double speed operations. Table 1 Basic Characteristics of Digital Filter Pass-Band Ripple Standard operation Double speed operation Transient Bandwidth 20.0 k~24.1 kHz 20.0 k~24.1 kHz Attenuation 0.11dB 0.11dB -26dB or less -26dB or less The characteristics of the digital filter frequencies are shown below. Figure 3 Digital Filter Frequency Characteristics (fs = 44.1 kHz) 5 2006-04-27 TC9404FNG 4. De-Emphasis Filter The built-in digital de-emphasis circuit is available for three kind of sampling frequency, fs of 32 kHz, 44.1 kHz, and 48 kHz. These setting controlled in the parallel mode ( P/ S = "H") with the LATCH (BS) pin (pin 18) and SHIFT (EMP) pin (pin 19). This is set in the serial mode ( P/ S = "L") with a microcontroller or other equipment. (refer to 9-2 microcontroller setting mode for further details on serial mode settings.) Table 2 De-Emphasis Filter Setting (when in the parallel mode) LATCH (BS) SHIFT (EMP) MODE (fs SELECT) H H 32 H L 48 L H 44.1 L L OFF (kHz) The digitalization of the de-emphasis filter eliminates the need for such external components as resistors, condensers and analog switches. In addition to this, the coefficients are aligned to reduce error in the de-emphasis filter characteristics. The filter structure and characteristics are shown below. Transfer function: H (Z) = (b0 + b1Z-1) (1 - a1Z -1) T1 = 50 s, T2 = 15 s Figure 4 IIR Digital De-Emphasis Filter Figure 5 Filter Characteristics 5. DA Conversion Circuit The IC incorporates a 2'nd - modulation DA converter for two channels (simultaneous output type). The internal structure of this is shown in Figure 6. 2'nd - converter: Y (Z) = X (Z) + (1 - Z- ) Q (Z) 12 Figure 6 - Modulation DA Converter 6 2006-04-27 TC9404FNG The - modulation clock has been designed to operate at 192 fs. The noise shaping characteristics are shown in Figure 7. Figure 7 Noise Shaping Characteristics 6. Data Output Circuit The output circuit is equipped with a 3'rd analog low-pass filter. This enables direct analog signals to be acquired from the IC's RO (pin 5) and LO (pin 9) output pins. Figure 8 Analog Filter Circuit 7 2006-04-27 TC9404FNG 7. Soft Mute Circuit The IC is equipped with a soft mute function, and this enables a soft mute to be set for the DA converter output by switching the SM pin (pin 18) from the "L" level to the "H" level when in the parallel mode ( P/ S = "H"). The soft mute's ON/OFF function and the DA converter output are shown in Figure 9. The Soft mute ON/OFF control function is disabled during level transition. Figure 9 Changes in The Soft Mute DA Converter Output Level 8. Common left Channel/Right Channel Digital Zero Data Detection Output Circuit The IC is equipped with a common left channel/right channel digital zero data detection output circuit, and the ZD pin (pin 11) is switched from "L" to "H" when data for both the left channel and the right channel becomes zero data for approximately 350 ms or longer. This is fixed at "L" when the data for the left channel and right channel is not zero data. 9. Description of Internal Control Signals The P/ S pin can be used to switch between the parallel mode ( P/ S pin = "H" in DC setting mode) and the serial mode ( P/ S pin = "L" with the microcontroller interface function). 9-1 Parallel Mode ( P/ S = "H": DC setting mode) Pins 18, 19 and 20 are used as the mode setting pins shown in the table below when in the parallel mode. Table 3 Pin Names at the Parallel Mode Pin No. 18 19 20 Pin Name BS EMP SM Function De-emphasis filter mode select pin De-emphasis filter control pin Soft mute control pin 8 2006-04-27 TC9404FNG 9-2 Serial Mode ( P/ S = "L": microcontroller setting mode) It is possible to make the various settings with a microcontroller when in the serial mode. Pins 18, 19 and 20 are used as the command input pins shown in the table below when in the serial mode. Table 4 Pin Names at The Serial Mode Pin No. 18 19 20 Pin Name LATCH SHIFT ATT Data latch signal input pin Shift clock signal input pin Data input pin Function The LATCH signals and ATT signals are loaded to the LSI internal shift registers on the SHIFT signal rising edge. It is consequently necessary for the data input from the ATT pin on the shift signal rising edge to be valid as indicated in the timing example in Figure 10. It is also necessary for the LATCH pulse to rise at least 1.5 s after the final clock rising edge input from the SHIFT pin. Operating the shift clock with LATCH low destabilizes the internal state, which may lead to malfunctions, so it must therefore be set to the low level after loading D7 to the register. A = 1.5 s or higher, B = 1.5 s or higher Figure 10 Example of Data Setting Timing in the Serial Mode The various control settings when in the serial mode are shown in the table below. Ensure that all control bits are set when the power supply is turned on. Table 5 Serial Mode Control Settings Serial Input Data D7 D6 D5 D4 D3 D2 D1 D0 Control Signal 0 AT6 AT5 AT4 AT3 AT2 AT1 AT0 1 BS EMP AT0~6: Attenuation level setting BS: De-emphasis mode select EMP: De-emphasis ON/OFF switch 9 2006-04-27 TC9404FNG (1) Digital attenuator The digital attenuation command is enabled when D7 = "L". The attenuation data can be set in 128 different ways. The relationship with the command's output is shown below. Table 6 Attenuation Data/Audio Data Output Audio Output -0.000dB -0.069dB : -42.076dB - Attenuation Data D6~D0 7F (HEX) 7E (HEX) : 01 (HEX) 00 (HEX) 01 (HEX) to 7E (HEX): The attenuation value is obtained with the following equation. ATT = 20 og (input data/127) dB Example: In case of attenuator = 7 A ATT = 20 og (122/127) dB = -0.349dB (2) Digital de-emphasis filter The Digital De-emphasis setting mode is enabled when D7 = "H". Controlled with EMP and BS signal. Table 7 Digital De-Emphasis Filter Setting BS EMP Mode H H 32 H L 48 L H 44.1 L L OFF (kHz) 10 2006-04-27 TC9404FNG Absolute Maximum Ratings (Ta = 25C) Characteristics Symbol VDD Supply voltage VDA VDX Input voltage Power dissipation Operating temperature Storage temperature Vin PD Topr Tstg Rating -0.3~6.0 -0.3~6.0 -0.3~6.0 -0.3~VDD + 0.3 200 -35~85 -55~150 V mW C C V Unit Electrical Characteristics (unless otherwise specified, Ta = 25C, VDD = VDX = VDA = 5 V) DC Characteristics Characteristics Symbol VDD Operating supply voltage (1) VDX VDA VDD Operating supply voltage (2) VDX VDA Power dissipation "H" level Input voltage "L" level Input current "H" level "L" level VIL IIH IIL IDD VIH Ta = -15~55C Operation frequency 12 MHz < fopr < 18.5 MHz = = XI = 16.9 MHz Ta = -35~85C Test Circuit Test Condition Min 4.5 4.5 4.5 2.7 2.7 2.7 VDD x 0.7 0 -10 Typ. 5.0 5.0 5.0 3.0 3.0 3.0 12 Max 5.5 5.5 5.5 5.5 5.5 5.5 20 VDD VDD x 0.3 10 V mA V V Unit A 11 2006-04-27 TC9404FNG AC Characteristics (over-sampling ratio = 192 fs) Characteristics Symbol Test Circuit 1 Test Condition 1 kHz sine wave, full-scale input VDD = VDX = VDA = 5.0 V Table harmonic distortion + noise 2 S/N ratio Dynamic range Cross-talk THD + N2 S/N DR CT 1 1 1 1 1 kHz sine wave, full-scale input VDD = VDX = VDA = 3.0 V 1 kHz sine wave, -60dB input conversion 1 kHz sine wave, full-scale input 1 kHz sine wave, full-scale input VDD = VDX = VDA = 5.0 V Analog output level 2 Operating frequency Input frequency Rise time Fall time Delay time Aout 2 fopr fLR fBCK tr tf td 1 1 kHz sine wave, full-scale input VDD = VDX = VDA = 3.0 V VDD = VDA = VDX > 4.5 V = LRCK duty cycle = 50% BCK duty cycle = 50% LRCK, BCK (10%~90%) BCK Edge LRCK, DATA 10 30 0.96 16.9344 Min Typ. Max Unit Table harmonic distortion + noise 1 THD + N1 -85 -80 dB 88 90 -85 96 95 -95 -78 -90 dB dB dB dB Analog output level 1 Aout 1 1 1250 mVrms 750 18.5 100 4.3 15 15 40 mVrms MHz kHz MHz ns ns ns 44.1 2.1168 Test Circuit-1: With the Use of a Sample Application Circuit SG: ANRITSU MG-22A or equivalent LPF: SHIBASOKU 725C built-in Filter Distortion factor gauge: SHIBASOKU 725C or equivalent Measuring Item THD + N, CT S/N, DR Distortion Factor Gauge Filter Setting A Weight OFF ON A weight: IEC-A or equivalent 12 2006-04-27 TC9404FNG AC Characteristics Stipulated Point (input signal stipulation: LRCK, BCK, DATA) Application Circuit TC9404F NG 13 2006-04-27 TC9404FNG Package Dimensions P-SSOP24-300-0.65A (Note) Sn-Ag plate Weight: 0.14 g (typ.) 14 2006-04-27 TC9404FNG RESTRICTIONS ON PRODUCT USE * The information contained herein is subject to change without notice. 021023_D 060116EBA * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E About solderability, following conditions were confirmed * Solderability (1) Use of Sn-37Pb solder Bath * solder bath temperature = 230C * dipping time = 5 seconds * the number of times = once * use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath * solder bath temperature = 245C * dipping time = 5 seconds * the number of times = once * use of R-type flux 15 2006-04-27 |
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